A New Era for Edge AI: Codasip’s Custom Vector Processor Drives the SYCLOPS Mission

The demand for Artificial Intelligence applications is not just growing – it’s skyrocketing, reshaping industries from autonomous transportation and advanced medical diagnostics to intelligent manufacturing and personalized education. As these AI models become increasingly sophisticated, the hunger for more efficient, powerful, and accessible hardware solutions intensifies. This critical juncture, where...

Codasip

Risc-v

Edge

Acceleration

event 04/22/2025

Beyond design automation: How we manage processor IP variants with Codasip Studio

If you’ve been following us at Codasip, you know we’re all about enabling Custom Compute. The power to shape processor hardware to get the best out of your software is, as we see it, key to standing out and getting that crucial edge in performance, power, and area. A big...

Unlock early software development for custom RISC-V designs with faster simulation

When designing complex Systems-on-Chip, software teams should be involved early in the process. This will help identify architectural bottlenecks, validate system behavior, and accelerate the entire project timeline. In this process, processor simulation models play a crucial role.

SYCLOPS GenVectorX

CERN hosts the world’s largest particle accelerator, the LHC, where beams of particles are accelerated and made to collide to study the fundamental structures of our universe. The LHC produces petabytes of physics data regarding particle collisions that need to be analysed efficiently. These collisions are expressed as operations on...

Syclops

Genvectorx

event 11/20/2024

Neural networks and human-to-human interfaces at Embedded World 2025

Someone asked me how many Embedded Worlds I’ve attended, and I honestly couldn’t give an exact answer. Is it 10? 12? 15? I’m not sure, but one thing’s for certain: I’m always excited to return. So, what makes this event so special? It’s not just the technical innovations that continue...

Cosmic Compute at the RISC-V Summit North America Hackathon

We, Codasip had the pleasure of sponsoring and hosting a hackathon at the RISC-V Summit North America 2024 in Santa Clara, California. As part of our commitment to advancing CPU design, we invited participants to take on a challenging technical mission that tested their skill through Codasip Studio, our advanced...

Solving the RISC-V puzzle: optimal performance with zero risk

This blog post summarizes a keynote presentation by our CEO Ron Black at the RISC-V Summit Europe 2024. You can watch a recording of the keynote presentation on RISC-V International’s YouTube channel.

Part Two - Porting AI codes from CUDA to SYCL and oneAPI, one llama at a time

Prelude In our first part we looked at the conversion from CUDA to SYCL via the whole project migration tool, SYCLomatic. Now we are going to take this portable code, and run it across an NVIDIA and Intel GPU. Building on the NVIDIA system Now we are going to build...

Part One - Porting AI codes from CUDA to SYCL and oneAPI, one llama at a time

Introduction The rapid advancement of LLMs can be attributed to their ability to effectively tackle complex problems, such as those encountered in chatbots, virtual assistants, content generation, and language translation. Their performance, which matches human capabilities, places LLMs at the forefront of AI models. The classical general purpose graph frameworks...

Accelom and SYCLOPS

Due to significant improvements in genomic sequencing technology, it is now possible to sequence a full human genome for less than $1000 and receive genetic data on several molecular levels of the cell (genomic, transcriptome, protein expression, copy-number variations, and so on). However, in order to turn this genomic Big...

Accelom

Syclops

event 07/16/2024

DAC 2024 – Showcasing the future of RISC-V through EDA

This week, the 2024 edition of RISC-V Summit Europe took place in lovely Munich, Germany. Those of us who attended last year’s edition in Barcelona might not have expected the same weather but Munich was up for the challenge and served us a sunny, hot week, only interrupted by a...

Sunny skies and electric energy: RISC-V Summit Europe 2024 shines in Munich

As I sat on the plane in Boston it’s fair to say that I was curious about what DAC 2024 would bring. The previous year was much better than I expected but a cold June in San Francisco wasn’t exactly what I was dreaming about. Afterall, while I was heading...

AdaptivePerf and SYCLOPS

AdaptivePerf is an open-source architecture-agnostic code profiler for Linux, based on the custom-patched “perf”. Using just one single command adaptiveperf "<command to be profiled>", the tool: samples both on-CPU and off-CPU activity, traces every spawned thread and process, minimises the risk of broken profiled stacks by detecting inappropriate kernel and...

Seven EU Projects Collaborate Around Shared Mission to Extract Meaningful Insights from Extreme Data

As part of the Horizon Europe funding programme, seven pioneering projects have received funding to address the challenges posed by extreme data generated by IoT, industrial, business, administration, environmental, scientific and societal sources. These projects are pursuing innovative approaches that integrate cutting-edge technologies, including Artificial Intelligence (AI), Internet of Things...

The oneAPI Construction Kit and SYCLOPS

With software evolving quickly, it has become increasingly common for hardware vendors to create specialist AI processors that run their software more efficiently than would be possible with out-of-the-box hardware. While these custom processors can offer the advantage of performance, they come with challenges for developers. Primary among these is...

Oneapi

Construction-kit

event 04/04/2024

Custom Compute for Edge AI: Accelerating innovation with Lund University and Codasip University Program

In recent years, the rapid advancement and adoption of Artificial Intelligence (AI) on the edge has brought about a surge in development. As AI models like ChatGPT become more prevalent and accurate, the computational requirements for inference also escalate. This necessitates architectural innovations aimed at reducing both power consumption and...

A custom RISC-V vector instruction to accelerate structured-sparse matrix multiplications

A novel AI-acceleration paper presents a method to optimize sparse matrix multiplication for machine learning models, particularly focusing on structured sparsity. Structured sparsity involves a predefined pattern of zero values in the matrix, unlike unstructured sparsity where zeros can occur anywhere. The research was conducted by Democritus University of Thrace...

Effectively hiding sensitive data with RISC-V Zk and custom instructions

Cryptographic hash functions play a critical role in computer security providing a one-way transformation of sensitive data. Many information-security applications benefit from using hash functions, specifically digital signatures, message authentication codes, and other forms of authentication. The calculation of hash functions such as SHA512, SHA256, MD5 etc is a potential...

Introducing the SYCLOPS Consortium

Announced in May this year, the SYCLOPS Project brings together 8 leading organizations from across Europe, collaborating to democratize AI acceleration and break the existing monopoly on the acceleration market. Our combined vision is using open standards to enable a healthy, competition-driven ecosystem with widespread adoption of both RISC-V®, an...

Consortium

Announcement

event 10/17/2023

Codasip 700 RISC-V processor family: Bringing the world of Custom Compute to everyone

Today, technology innovators must have new ways to create differentiated products. How are they supposed to meet the demand for more computational performance when semiconductor scaling laws are showing their limits? There is only one way: having a compute that is custom for specific needs. And what do we need...

Codasip

Risc-v

event 08/31/2023

How the SYCLOPS project democratizes AI acceleration

Codasip Labs is all about innovation, and specifically the commercialization of that innovation. Naturally, with the rise of Artificial Intelligence (AI) and Machine Learning (ML), these areas have become a key focus for us. At the beginning of 2023, we joined the New Horizon Europe Project SYCLOPS (Scaling extreme analYtics...

Codasip

Risc-v

event 07/25/2023

Re-targetable LLVM C/C++ compiler for RISC-V

RISC-V is a modular instruction set architecture (ISA) with great customization capabilities that enable innovation and differentiation without fragmentation. On top of the baseline modules from ratified/standard ISA extensions, such as integer instructions or floating-point instructions, designers can add custom instructions: pure design freedom! And the reasons for adding instructions...

No one-size-fits-all approach to RISC-V processor optimization

As the demand for high-performance processors continues to grow and semiconductor scaling laws continue to show their limits, the need for processor optimization is inevitable. As I explained in a previous blog, RISC-V is designed to enable this. However, there is no one-size-fits-all approach to processor optimization. As each workload...

Launch of the New Horizon Europe Project SYCLOPS

8 leading European organisations join forces to bring together RISC-V and SYCL standards to demonstrate ground-breaking advances in scalability of extreme data analytics via fully-open AI acceleration The wide-spread adoption of AI has resulted in a market for novel hardware accelerators that can efficiently process AI workloads. Unfortunately, all popular...

Launch

Update

event 05/02/2023

RISC-V customization, HW/SW co-optimization, and custom compute

Do we still need to introduce and define RISC-V? You know, the open-source instruction set architecture (ISA) that is gaining popularity thanks to its flexibility, scalability, and modularity. Okay, we just did, just to be sure we are all on the same page. One of the key benefits and the...

Codasip

Risc-v

Customization

publicSocials

Twitter/X

newspaperUpdates

A New Era for Edge AI: Codasip’s Custom Vector Processor Drives the SYCLOPS Mission

Beyond design automation: How we manage processor IP variants with Codasip Studio

If you’ve been following us at Codasip, you know we’re all about enabling Custom Compute. The power to shape processor hardware to get the best out of your software is, as we see it, key to standing out and getting that crucial edge in performance, power, and area. A big...

Unlock early software development for custom RISC-V designs with faster simulation

When designing complex Systems-on-Chip, software teams should be involved early in the process. This will help identify architectural bottlenecks, validate system behavior, and accelerate the entire project timeline. In this process, processor simulation models play a crucial role.

SYCLOPS GenVectorX

Neural networks and human-to-human interfaces at Embedded World 2025

Someone asked me how many Embedded Worlds I’ve attended, and I honestly couldn’t give an exact answer. Is it 10? 12? 15? I’m not sure, but one thing’s for certain: I’m always excited to return. So, what makes this event so special? It’s not just the technical innovations that continue...

Cosmic Compute at the RISC-V Summit North America Hackathon

Solving the RISC-V puzzle: optimal performance with zero risk

This blog post summarizes a keynote presentation by our CEO Ron Black at the RISC-V Summit Europe 2024. You can watch a recording of the keynote presentation on RISC-V International’s YouTube channel.

Part Two - Porting AI codes from CUDA to SYCL and oneAPI, one llama at a time

Prelude In our first part we looked at the conversion from CUDA to SYCL via the whole project migration tool, SYCLomatic. Now we are going to take this portable code, and run it across an NVIDIA and Intel GPU. Building on the NVIDIA system Now we are going to build...

Part One - Porting AI codes from CUDA to SYCL and oneAPI, one llama at a time

Accelom and SYCLOPS

DAC 2024 – Showcasing the future of RISC-V through EDA

This week, the 2024 edition of RISC-V Summit Europe took place in lovely Munich, Germany. Those of us who attended last year’s edition in Barcelona might not have expected the same weather but Munich was up for the challenge and served us a sunny, hot week, only interrupted by a...

Sunny skies and electric energy: RISC-V Summit Europe 2024 shines in Munich

As I sat on the plane in Boston it’s fair to say that I was curious about what DAC 2024 would bring. The previous year was much better than I expected but a cold June in San Francisco wasn’t exactly what I was dreaming about. Afterall, while I was heading...

AdaptivePerf and SYCLOPS

Seven EU Projects Collaborate Around Shared Mission to Extract Meaningful Insights from Extreme Data

The oneAPI Construction Kit and SYCLOPS

Custom Compute for Edge AI: Accelerating innovation with Lund University and Codasip University Program

A custom RISC-V vector instruction to accelerate structured-sparse matrix multiplications

Effectively hiding sensitive data with RISC-V Zk and custom instructions

Introducing the SYCLOPS Consortium

Codasip 700 RISC-V processor family: Bringing the world of Custom Compute to everyone

How the SYCLOPS project democratizes AI acceleration

Re-targetable LLVM C/C++ compiler for RISC-V

No one-size-fits-all approach to RISC-V processor optimization

Launch of the New Horizon Europe Project SYCLOPS

RISC-V customization, HW/SW co-optimization, and custom compute

Do we still need to introduce and define RISC-V? You know, the open-source instruction set architecture (ISA) that is gaining popularity thanks to its flexibility, scalability, and modularity. Okay, we just did, just to be sure we are all on the same page. One of the key benefits and the...

publicSocials

Cookies

newspaperUpdates

A New Era for Edge AI: Codasip’s Custom Vector Processor Drives the SYCLOPS Mission

Beyond design automation: How we manage processor IP variants with Codasip Studio

If you’ve been following us at Codasip, you know we’re all about enabling Custom Compute. The power to shape processor hardware to get the best out of your software is, as we see it, key to standing out and getting that crucial edge in performance, power, and area. A big...

Unlock early software development for custom RISC-V designs with faster simulation

When designing complex Systems-on-Chip, software teams should be involved early in the process. This will help identify architectural bottlenecks, validate system behavior, and accelerate the entire project timeline. In this process, processor simulation models play a crucial role.

SYCLOPS GenVectorX

Neural networks and human-to-human interfaces at Embedded World 2025

Cosmic Compute at the RISC-V Summit North America Hackathon

Solving the ​RISC-V puzzle: optimal performance with zero risk

This blog post summarizes a keynote presentation by our CEO Ron Black at the RISC-V Summit Europe 2024. You can watch a recording of the keynote presentation on RISC-V International’s YouTube channel.

Part Two - Porting AI codes from CUDA to SYCL and oneAPI, one llama at a time

Prelude In our first part we looked at the conversion from CUDA to SYCL via the whole project migration tool, SYCLomatic. Now we are going to take this portable code, and run it across an NVIDIA and Intel GPU. Building on the NVIDIA system Now we are going to build...

Part One - Porting AI codes from CUDA to SYCL and oneAPI, one llama at a time

Accelom and SYCLOPS

DAC 2024 – Showcasing the future of RISC-V through EDA

This week, the 2024 edition of RISC-V Summit Europe took place in lovely Munich, Germany. Those of us who attended last year’s edition in Barcelona might not have expected the same weather but Munich was up for the challenge and served us a sunny, hot week, only interrupted by a...

Sunny skies and electric energy: RISC-V Summit Europe 2024 shines in Munich

As I sat on the plane in Boston it’s fair to say that I was curious about what DAC 2024 would bring. The previous year was much better than I expected but a cold June in San Francisco wasn’t exactly what I was dreaming about. Afterall, while I was heading...

AdaptivePerf and SYCLOPS

Seven EU Projects Collaborate Around Shared Mission to Extract Meaningful Insights from Extreme Data

The oneAPI Construction Kit and SYCLOPS

Custom Compute for Edge AI: Accelerating innovation with Lund University and Codasip University Program

A custom RISC-V vector instruction to accelerate structured-sparse matrix multiplications

Effectively hiding sensitive data with RISC-V Zk and custom instructions

Introducing the SYCLOPS Consortium

Codasip 700 RISC-V processor family: Bringing the world of Custom Compute to everyone

How the SYCLOPS project democratizes AI acceleration

Re-targetable LLVM C/C++ compiler for RISC-V

No one-size-fits-all approach to RISC-V processor optimization

Launch of the New Horizon Europe Project SYCLOPS

RISC-V customization, HW/SW co-optimization, and custom compute

Do we still need to introduce and define RISC-V? You know, the open-source instruction set architecture (ISA) that is gaining popularity thanks to its flexibility, scalability, and modularity. Okay, we just did, just to be sure we are all on the same page. One of the key benefits and the...

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Solving the RISC-V puzzle: optimal performance with zero risk